The International Arab Journal of Information Technology (IAJIT)


Efficient Mapping Algorithm on Mesh-based NoCs in Terms of Cellular Learning Automata

Network-on-Chip (NoC) presents the interesting approaches to organize complex communications in many systems. NoC can also be used as one of the effective solutions to cover the existing problems in System-on-Chip (SoC) such as scalability and reusability. The most common topology used in NoC is mesh topology. However, offering the mapping algorithm for mapping applications, based on weighted task graphs, onto the mesh is known as a NP-hard problem. This paper presents an effective algorithm called ‘Boundary Mapping Algorithm’ (BMA), in terms of decreasing the priority of low weighted edges in the task graph to improved performance in the NoCs. A low complexity mapping algorithm cannot present the optimal mapping results for all applications. Then, adding an optimization phase to mapping algorithms can have a positive impact on their performance. So, this study presents an optimization phase based on Cellular Learning Automata to achieve this goal. For the evaluation mapping algorithm and optimization phase, we compared the BMA method with Integer Linear Programming (ILP), Nmap, CastNet and Onyx methods for six real applications. The mapping results indicated that the proposed algorithm can be useful for some applications. Also, optimization phase can be useful for the proposed and other mapping algorithms.

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[20] Wolfram S., “Universality and Complexity in Cellular Automata,” Physica D: Nonlinear Phenomena, vol. 10, no. 1-2, pp. 1-35, 1984. 322 The International Arab Journal of Information Technology, Vol. 16, No. 2, March 2019 Mohammad Keley was born in Dezful. He received hir B.Sc. degree in Computer Engineering from Islamic Azad University, Dezfoul branch, Iran in 2003, and his M.Sc. degree in Computer Architecture Engineering from Science and Research Islamic Azad University, Tehran, Iran, in 2006. His research interests include design and analysis of reliable, fault tolerant and mapping in Network-on-Chips and 3- Dimentional Network-on-Chip interconnections. Ahmad Khademzadeh was born in Mashhad, Iran, in 1943. He received the B.Sc. degree in applied physics from Ferdowsi University, Mashhad, Iran, in 1969 and the M.Sc., Ph.D. degrees respectively in Digital Communication and Information Theory & Error Control Coding from the University of Kent, Canterbury, UK. He is currently the Head of Education & National Scientific and International Scientific Cooperation Department at ICT Research Institute (ITRC). He was the head of Test Engineering Group and the director of Computer and Communication Department at ITRC. He is also a lecturer at Tehran Universities & he is a committee member of the Iranian Electrical Engineering Conference Permanent Committee. Dr. Khadem-Zadeh has been received four distinguished national and international awards including Kharazmi International Award, and has been selected as the National outstanding researcher of the Iran Ministry of Information and Communication Technology. Mehdi Hosseinzadeh was born in Dezful in 1981. He received his B.Sc. degree in Computer Hardware Engineering from Islamic Azad University, Dezful branch, Iran in 2003. He also received his M.Sc. and Ph.D. degrees in Computer System Architecture from the Science and Research Branch, Islamic Azad University, Tehran, Iran in 2005 and 2008, respectively. He is currently an assistant professor in Department of Computer Engineering of Science and Research Branch of Islamic Azad University, Tehran, Iran. His research interests are computer arithmetic with emphasis on residue number system, cryptography, network security and e-commerce.