Abstract Design of a topology and its router plays a vital role in a 3D Network-on-Chip (3D NoC) architecture. In this paper, we develop a partially vertically connected topology, so called 3D Recursive Network Topology (3D RNT) and using an analytical model, we study the performance of the 3D RNT. Delay per Buffer Size (DBS) and Chip Area per Buffer Size (CABS) are the parameters considered for the performance evaluation. Our experimental results show that the vertical links are cut down upto 75% in 3D RNT compared to that of 3D Fully connected Mesh Topology (3D FMT) at the cost of increasing DBS by 8%, besides 10% lesser CABS is observed in the 3D RNT. Further, a Programmable Prefix router-Arbiter (PPA) is designed for 3D NoC and its performance is analyzed. The results of the experimental analysis indicate that PPA has lesser delay and area (gate count) compared to Round Robin Arbiter (RRA) with prefix network.

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[16] Viswanathan N., Paramasivam K., and Somasundaram K., Performance and Cost Metrics Analysis of a 3D NoC Topology Using Network Calculus, Applied Mathematical Sciences, vol. 7, no. 84, pp. 4173-4184, 2013. Nallasamy Viswanathan received his bachelor degree in electronics and communication engineering from Bharathiar University, Coimbatore, Tamilnadu, India in 1995. He earned his master degree in communication systems and Ph.D. from Anna University, Chennai, Tamil Nadu in 2007 and 2014 respectively. Currently he is working as a professor in the department of electronics and communication engineering, Mahendra Engineering College, Namakkal, Tamil Nadu, India. His research interests include VLSI design, computer networks and Network-on-Chip. Kuppusamy Paramasivam presently with Karpagam College of Engineering (Autonomous), Coimbatore, India as Professor and Head, ECE Department. He completed UG (BE-ECE with Distinction), PG (ME-AE) from Bharathiar University during 1995 and 1996. He completed his Ph.D. degree (Highly Commended) at PSG college of Technology, Coimbatore, India. He has around 20 years of teaching experience with 13 years of research experience. He has published 78 research papers in Journals and Conferences. His areas of interest are Microprocessors, VLSI Design, Low power VLSI testing and Network on Chip(NOC). Kanagasabapathi Somasundaram received MS degree in Mathematics from St, Joseph s College, Trichy, India, in 1995 and a doctoral degree in mathematics from Bharathiar University, Coimbatore, India, in 2003. He completed his post doctoral research fellowship from Turku Centre for computer science, University of Turku, Finland, in 2009. Currently he is professor in the department of mathematics, Amrita Vishwa Vidyapeetham, Coimbatore, India. His research interests include linear algebra, graph theory and network on chip Annexure A Performance comparison of PPA with RRA Parameters RRA Port 2 PPA Port 2 RRA Port 4 PPA Port 4 RRA Port 8 PPA Port 8 RRA Port 16 PPA Port 16 Number of Slice Flip Flops 1 1 2 2 3 3 7 4 Number of 4 input LUTs 3 3 21 19 66 58 144 143 Number of occupied Slices 2 2 11 10 35 30 77 75 gate count for design 29 29 154 139 432 381 944 899 Maximum Frequency in Mhz 467 467 163 241 90 117 75 80 Maximum .Delay in ns 6.34 6.34 8.68 7.85 11.49 9.83 12.31 11.37 Memory Usage in MB 134 134 134 134 135 135 136 135 Power consumption in mW 104 104 93 95 92 95 96 97