Abstract  In  this  paper,  we  introduced  a  Discrete  Wavelet  Tra nsform  (DWT)  based  VLSI-oriented  lossy  image  compre ssion  approach,  widely  used  as  the  core  of  digital  image  compression.  Here,  Distributed  Arithmetic  (DA)  tech nique  is  applied  to  determine  the  wavelet  coefficients,  so  that  the  num ber  of  arithmetic  operation  can  be  reduced  substant ially.  As  well,  the  compression rate is enhanced with the aid of introd ucing RW block that blocks some of the coefficients obtained from the high  pass  filter  to  zero.    Subsequently,  Differential  Pu lse-Code  Modulation  (DPCM)  and  huffman-encoding  are   applied  to  acquire  the  binary  sequence  of  the  image.  The  functional  si mulation  of  each  module  is  presented  as  well  as  the   performance  of  each  module  is  widely  analyzed  with  gate  required,  clock   cycles  required,  power,  processing  rate,  and  processing  time.  From  the  analysis,  it  is  found  that  the  DCM  module  requires  more  gates  to  do  the  transformation  process  compare d  to  other  modules.  Eventually, the proposed compression approach is co mpared with the existing methods in terms of processor area and power.  Comparative  result  shows  that  the  proposed  method  o ffers  good  performance  in  power-efficiency  corresponding  to  0.328  mW/chip than the prior methods.   

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[39] Uzun I. and Amira A., Real2Time 22D Wavelet Transform Implementation for HDTV Compression, Real-Time Imaging , vol. 11, no. 2, pp. 1512165, 2005. 68 The International Arab Journal of Information Technology, Vol. 11, No. 1, January 2014 Devangkumar Shah obtained his Bs degree in electrical engineering from Gujarat University, India in 1999. Then he obtained his Ms degree in microprocessor system applications from the MS University of Baroda, India in 2008. Currently, he is a assistant professor at the School of Engineering, R K University, India. His specializations include blue tooth network, networking, and virtual reality. His curre nt research interests are digital signal and image processing, microprocessor, embedded systems and VLSI. Chandresh Vithlani obtained his Bs degree in electronics and communication engineering from Gujarat University, India in 1991. Then he obtained his Ms degree in electronics and communication engineering from Gujarat University, India in 1998 and PhD degree in electronics communication from Gujarat University in the year 2006. Currently, he is working as an associate professor in the Department of Electronics Communication Engineering, Government. Engineering College, India. He has published number of papers in national and international conferences and journals. His current research areas of interests a re microprocessor, embedded systems, digital signal an d image processing.