Fault tolerant circuits are currently required in several major application sectors. Besides and in complement to other possible approaches such as proving or analytical modeling whose applicability and accuracy are significantly restricted in the case of complex fault tolerant systems, fault-injection has been recognized to be particularly attractive and valuable. Fault injection provides a method of assessing the dependability of a system under test. It involves inserting faults into a system and monitoring the system to determine its behavior in response to a fault. Several fault injection techniques have been proposed and practically experimented. They can be grouped into hardware-based fault injection, software-based fault injection, simulation-based fault injection, emulation-based fault injection and hybrid fault injection. This paper presents a survey on fault injection techniques with comparison of the different injection techniques and an overview on the different tools.

[1] Aidemark J., Vinter J., Folkesson P., and Karlsson J., “GOOFI: Generic Object-Oriented Fault Injection Tool,” in Proceedings of International Conference on Dependable Systems and Networks (DSN'2001), Gothenburg, Sweden, July 2001.

[2] Amendola A., Impagliazzo L., Marmo P., and Poli F., “Experimental Evaluation of Computer- Based Railway Control Systems,” in Proceedings of 27th International Symposium on Fault- Tolerant Computing (FTCS-27), Seattle, WA, USA, pp. 380-384, June 1997.

[3] Arlat J., “Validation de la Sûreté de Fonctionnement Par Injection de Fautes. Méthode Mise en Œuvre et Application,” Thèse Présentée à l’INP Toulouse, Rapport de Recherche LAAS, no. 90-399, December 1990.

[4] Baraza J. C., Gracia J., Gil D., and Gil P. J., “A Prototype of a VHDL-Based Fault Injection Tool,” in Proceedings of DFT'2000 Conference, pp. 396-404, October 2000.

[5] Benso A., Prinetto P., Rebaudengo M., and Reorda M., “EXFI: A Low-Cost Fault Injection System for Embedded Microprocessor-Based Boards,” ACM Transactions on Design Automation of Electronic Systems, vol. 3, no. 4, pp. 626-634, October 1998.

[6] Carreira J., Madeira H., and Silva J., “Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers,” IEEE Transactions on Software Engineering, vol. 24, no. 2, pp. 125-136, February 1998.

[7] Cheng K. T., Huang S. Y., and Dai W. J., “Fault Emulation: A New Methodology for Fault Grading,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 18, no. 10, pp. 1487-1495, October 1999.

[8] Choi G. S. and Iyer R. K., “FOCUS: An Experimental Environment for Fault Sensitivity Analysis,” IEEE Transactions on Computers, vol. 41, no. 12, pp. 1515-1526, December 1992.

[9] Civera P., Macchiarulo L., Rebaudengo M., Reorda S. M., and Violante M., “Exploiting FPGA for Accelerating Fault Injection Experiments,” in Proceedings of 6th International On-Line Testing Workshop, Palma de Mallorca, Spain, July 2000.

[10] Delong T. A., Johnson B. W., and Profetan J. A., “A Fault Injection Technique for VHDL Behavioral-Level Models,” IEEE Design & Test of Computers, vol. 13, pp. 24-33, 1996.

[11] Entrena L., López C., and Olías E., “Automatic Generation of Fault Tolerant VHDL Designs in RTL,” FDL (Forum on Design Languages), Lyon, France, September 2001.

[12] Folkesson P., Svensson S., and Karlsson J., “A Comparison of Simulation Based and Scan Chain Implemented Fault Injection,” in Proceedings of 28th International Symposium on Fault-Tolerant Computing (FTCS-28), Munich, Germany, pp. 284-293, June 1998.

[13] Fuchs E., “An Evaluation of the Error Detection Mechanisms in MARS Using Software Implemented Fault Injection,” in Proceedings of 2nd European Dependable Computing Conference (EDCC-2), Taormina, Italy, October 1996.

[14] Gunneflo U., Karlsson J., and Johansson R., “Using Heavy-Ion Radiation to Validate Fault- Handling Mechanisms,” IEEE Micro, vol. 14, no. 1, pp. 8-23, February 1994.

[15] Guthoff J. and Sieh V., “Combining Software- Implemented and Simulation-Based Fault Injection into a Single Fault Injection Method,” in Proceedings of 25th Symposium on Fault- Tolerant Computing (FTCS), pp. 196-206, 1995.

[16] Han S., Rosenberg H., and Shin K., “DOCTOR: An Integrated Software Fault Injection Environment,” Technical Report CSE-TR-192- 93, University of Michigan, 1993.

[17] Hsueh M. C., Tsai T. K., and Iyer R. K., “Fault Injection Techniques and Tools,” IEEE Computer, vol. 30, no. 4, pp. 75-82, April 1997.

[18] Jenn E., Rimen M., Ohlsson J., Karlsson J., and Arlat J., “Design Guidelines of a VHDL-Based Simulation Tool for the Validation of Fault Tolerance,” in Proceedings of 1st ESPRIT Basic Research Project PDCS-2 Open Workshop, LAAS/CNRS, Toulouse, pp. 461-483, September 1993.

[19] Kanawati G. A., Kanawati N. A., and Abraham J. A., “FERRARI: A Tool for the Validation of System Dependability Properties,” in Proceedings of 22nd Annual International Symposium Fault-Tolerant Computing, IEEE CS Press, Los Alamitos, California, pp. 336-344, 1992.

[20] Leveugle R., “Fault Injection in VHDL Descriptions and Emulations,” in Proceedings of DFT'2000 Conference, pp. 414-419, October 2000.

[21] Leveugle R., Antoni L., and Feher B., “Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes,” in Proceedings of DFT'2000 Conference, November 2002.

[22] Madeira H., Rela M., Moreira F., and Silva J. G., “RIFLE: A General Purpose Pin-level Fault 186 The International Arab Journal of Information Technology, Vol. 1, No. 2, July 2004 Injector,” in Proceedings of 1st European Dependable Computing Conference (EDCC-1), (Berlin, Germany), Springer-Verlag, pp. 199- 216, 1994.

[23] Rebaudengo M., Benso A., Marmo P., and Impagliazzo L., “Fault-List Collapsing for Fault Injection Experiments,” in Proceedings of Annual Reliability and Maintainability Symposium (RAMS'98), pp. 383-388, January 1998.

[24] Rebaudengo M., Prrota B., Violante M., and Sonza R. M., “New Techniques for Accelerating Fault Injectioning VHDL Description,” in Proceedings of International On-Line Test Workshop (IOLTW'2000), Mallorca, Spain, pp. 61-66, July 2000.

[25] Rousselle C., Pflanz M., Behling A., Mohaupt T., and Vierhaus H. T., “A Register-Transfer-Level Fault Simulator for Permanent and Transient Faults in Embedded Processors,” in Proceedings of DATE'2001 Conference, Munich, Germany, 2001

[26] Segall Z., Vrsalovic D., Siewiorek D., Yaskin D., Kownacki J., Barton J., Dancey R., Robinson A., and Lin T., “FIAT-Fault Injection Based Automated Testing Environment,” in Proceedings of 18th International Symposium on Fault-Tolerant Computing (FTCS-18), pp. 102- 107, 1988.

[27] Sieh V., Tschäche O., and Balbach F., “VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions,” in Proceedings of 27th International Symposium on Fault-Tolerant Computing (FTCS-27), Seattle, WA, USA, pp. 32-36, June 1997.

[28] Sonza Reorda M., Berrojo L., González I., and Corno F., “New Techniques for Speeding-up Fault-Injection Campaigns,” in Proceedings of (DATE'2002) Design Automation and Test in Europe, Paris, France, pp. 847-852, March 2002.

[29] Stott D. T., Kalbarczyk Z., and Iyer R. K, “Using NFTAPE for Rapid Development of Automated Fault Injection Experiments,” Research Report, Center for Reliable and High-Performance Computing, University of Illinois at Urbana- Champaign, 1999.

[30] Tsai T. K. and Iyer R. K., “An Approach to Benchmarking of Fault-Tolerant Commercial Systems,” in Proceedings of 26th Annual International Symposium Fault-Tolerant Computing, IEEE CS Press, Los Alamitos, California, pp. 314-323, 1996.

[31] Yu Y., “A Perspective on the State of Research on Fault Injection Techniques,” Research Report, University of Virginia, May 2001. Haissam Ziade received his BSc in physics from Lebanese University in 1979, his engineering diploma from ENSERG in Grenoble France in 1982, and his PhD in engineering from INSA/ Toulouse in 1986. Since 1986, he has been in the Electrical and Electronics Department at the Lebanese University at Tripoli/Lebanon, where he is currently an associate professor. He is an assistant researcher at TIMA Laboratory (Grenoble, France) in “Qualification of Circuits” research group since 1986. His main research topics are the study of the test and validation of complex integrated circuits, the fault injection methodologies and the design with programmable circuits and systems. Rafic Ayoubi received his BSc degree in electrical engineering, the MSc and PhD degrees in computer engineering from the University of Louisiana, Lafayette, Louisiana in 1988, 1990, and 1995, respectively. He joined The University of Balamand, Tripoli, Lebanon, in 1996 where he is currently an assistant professor. Dr. Ayoubi's current research interests are parallel architectures, parallel algorithms, fault tolerance, artificial neural networks, and FPGA technology. In these areas, he published several research papers in several journals and conferences. He has received the first prize in the 2nd Annual Exhibition for Industrial Research Achievements in Lebanon. Raoul Velazco has been with CNRS (French Research Agency) since 1984. Leader at TIMA Laboratory (Grenoble, France) of “Qualification of Circuits” research group. His main research topics are the study of the effects of radiation on integrated circuits, the development of test methods for complex circuits (processors, microcontrollers,...) and the design of dedicated functional test systems. He has more than 170 publications, 32 of them in IEEE Transactions on Nuclear Science.