Abstract  Security  plays  an  important  role  in  many  embedded  s ystems.  All  security  based  algorithms  are  implemented  in  hardware  or  software,  and  on  physical  devices  which   interact  with  the  systems  and  influenced  by  their environments.  The  attacker  extracts,  investigate  and  monitor  these  ph ysical  interactions  and  extracts  side  channel  information  which  is  used  in  cryptanalysis. This type of cryptanalysis is known  as side channel cryptanalysis and attacks performed  by using this method is  known  side  channel  attacks.  There  are  different  typ es  of  side  channel  attacks  based  on  side  channel  in formation  like  time,  power,  electromagnetic  information  and  faulty  outpu t  emitted  from  the  cryptographic  devices  during  implementation.  The  attack  that  occurs  based  on  the  run-time  by  which  t he  information  gained  from  physical  characteristics  of  cryptosystems  to  retrieve  the  secret  key  is  known  as  the  timing  atta ck.  The  side  channel  attacks  are  vulnerable  to  both   symmetric  and  asymmetric  algorithms.  RSA  is  an  asymmetric  algorit hm  which  plays  an  important  role  in  most  of  the  applications,  but  this  algorithm  is  vulnerable  to  timing  attack.  So  a  new  technique  is  proposed  called  “Randomness  Algorithm”   and  Optical  Asymmetric  Encryption  Padding  (OAEP)  technique  to  i mprove  the  robustness  of  RSA  algorithm  against  timing  attack,  by  introducing randomness in computation of decryption  process to make the timing information unusable to the attacker.   

References

[1] Ali H. and Al-Salami M., Timing Attack Prospect for RSA Cryptanalysts Using Genetic Algorithm Technique, The International Arab Journal of Information Technology , vol. 1, no. 1, pp. 80-85, 2004.

[2] Aumuller C., Bier P., Fischer W., Hofreiter P., and Seifert J, Fault Attacks on RSA with CRT: Concrete Results and Practical Counter- Measures, in Proceedings of the 4 th International Workshop Redwood Shores , USA, pp. 260-275, 2002.

[3] Borst J, Block Ciphers: Design, Analysis and Side-Channel Analysis, PhD Thesis, K.U.Leuven, 2001.

[4] Chen C., Wang T., and Tian J., Improving Timing Attack on RSA-CRT via Error Detection and Correction Strategy, Information Sciences, vol.232, pp. 464-474, 2013.

[5] Giraud C., An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis, IEEE Transactions on Computers , vol. 55, no. 9, pp. 1116-1120, 2006.

[6] Kocher P., Timing Attack on Implementations of Diffie-Hellman, RSA, DSS, and other Systems, available at: http://courses.csail.mit.edu/ 6.857/2006/handouts/TimingAttacks.pdf, last visited 1996.

[7] Kocher P., Jaffe J., and Jun B., Differential Power Analysis, available at: https://www.rambus.com/differential-power- analysis/, last visited 1999.

[8] Kopf B. and Durmuth M., A Provably Secure and Efficient Countermeasure Against Timing Attack, in Proceeding of the 22 nd IEEE Computer Security Foundation Symposium , Port Jefferson, pp. 324-335, 2009.

[9] Shamir A., Improved Method and Apparatus for Protecting Public Key Schemes from Timing and Fault Attacks, available at: http://www.google.com/patents/US5991415, last visited 1999.

[10] Srivaths R., Anand R., Kocher P., and Hattangady S., Security in Embedded Systems: Design Challenges, ACM Transactions on Embedded Computing Systems , vol. 3, no. 3, pp. 461-491, 2004.

[11] Zhou Y. and Feng D., Side-Channel Attacks: Ten Years after its Publication and the Impacts on Cryptographic Module Security Testing, available at: http://eprint.iacr.org/2005/388.pdf, last visited 2005. Amuthan Arjunan currently, working as Associate Professor in the Department of Computer Science and Engineering, Pondicherry Engineering College, Puducherry. Completed his Under graduate BTech in Computer Science and Engineering from Pondicherry Engineering College, ME from College of Engineering, Anna University, and Chennai. He has obtained his doctorate in the area of Information Security at Pondicherry Engineering College under Pondicherry Universi ty. Praveena Narayanan currently, working as Assistant Professor in Department of Information Technology, Alpha College of Engineering and Technology, Puducherry. She completed BTech in Information Technology from Bharathiyar College of Engineering and Technology and MTech Information Security from Pondicherry Engineering College under Pondicherry University. Kaviarasan Ramu currently, working as Assistant Professor in Department of Computer Science and Engineering, Alpha College of Engineering and Technology, Puducherry. He completed BTech in Information Technology from Bharathiyar College of Engineering and Technology and MTech Information Security from Pondicherry Engineering College under Pondicherry University.