The International Arab Journal of Information Technology (IAJIT)


Configurable Hardware Implementations of Bulk Encryption Units for Wireless Communications

Hardware implementations of bulk encryption units for wireless communications are presented in this paper. These units are based on the Triple DES (TDES) block cipher. The hardware modules can be configured in order to implement either the TDES or the DES block cipher. Three different hardware implementations of TDES are proposed. The first two implementations are based on the pipeline design technique, while the third implementation uses the traditional feedback logic design technique (looping). In addition, the DES block cipher’s S-BOXes have been implemented by Look Up Tables (LUTs) and/or ROM blocks. Comparing with the LUTs, the ROM blocks implementation approach provides higher performance. But, the LUTs implementation approach is used in cases where the ROM blocks are not available. For high-speed performance applications the loop unrolling architecture is selected. The proposed implementation of this architecture achieves 7.36 Gbps data throughput whilst the 16-stage pipeline 2.45 Gbps. The implementation data throughput which is based on the looping architecture is 121 Mbps, but is used significant less hardware resources.


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[15] Xilinx, Virtex: 2.5 V Field Programmable Gate Arrays, available at www.xilinx. com/, San Jose, California, USA, 2001. Paris Kitsos received the BSc in physics from the University of Patras, Greece. He is currently pursuing his PhD in the Department of Electrical and Computer Engineering at the University of Patras. His research interests include VLSI design, hardware implementations of cryptography algorithms, security protocols for wireless communication systems, and Galois field arithmetic implementations. He has published many technical papers in the areas of his research. Odysseas Koufopavlou received the Diploma of electrical engineering in 1983 and the PhD degree in electrical engineering in 1990, both from University of Patras, Greece. From 1990 to 1994 he was at the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA. Currently, he is an associate professor with the ECE Department, University of Patras. His research interests include VLSI design, VLSI crypto systems, and high performance communication subsystems. Dr. Koufopavlou has published more than 90 technical papers and received patents and inventions in these areas. He served as general chairman for the IEEE ICECS’1999. 127 The International Arab Journal of Information Technology, Vol. 1, No. 1, January 2004